Carbon Nanotube Based Delay Model For High Speed Energy Efficient on Chip Data Transmission Using: Current Mode Technique

摘要

Speed is a major concern for high density VLSI networks. In this paper theclosed form delay model for current mode signalling in VLSI interconnects hasbeen proposed with resistive load termination. RLC interconnect line ismodelled using characteristic impedance of transmission line and inductiveeffect. The inductive effect is dominant at lower technology node is modelledinto an equivalent resistance. In this model first order transfer function isdesigned using finite difference equation, and by applying the boundaryconditions at the source and load termination. It has been observed that thedominant pole determines system response and delay in the proposed model. UsingCNIA tool (carbon nanotube interconnect analyzer) the interconnect lineparameters has been estimated at 45nm technology node. The novel proposedcurrent mode model superiority has been validated for CNT type of material. Itsuperiority factor remains to 66.66% as compared to voltage mode signalling.And current mode dissipates 0.015pJ energy where as VM consume 0.045pJ for asingle bit transmission across the interconnect over CNT material. Secondly thedamping factor of a lumped RLC circuit is shown to be a useful figure of merit.